Deep-Chip
GenAI-Driven SoC Design and Security
VerilogDB
The Largest, Highest-Quality Dataset for RTL Generation.
Explore →DeepV
Model-Agnostic RAG Framework for Verilog Code Generation.
Explore →Trusting the Machine
How Secure is LLM-Generated RTL Code?
Explore →SV-LLM
Agentic Approach for SoC Security Verification.
Explore →SoCureLLM
LLM-driven large-scale SoC security verification.
Explore →Empowering Hardware Security
Development of a Vulnerable Hardware Database.
Explore →LLM for SoC Security: A Paradigm Shift
A Look into the Future of Hardware Security.
Explore →Continuity in Security
Leveraging LLM for Translating Security Properties.
Explore →Rethinking SoC Verification
Secure Cross-Layer Interactions in System-on-Chips.
Explore →